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targets/efinix_t120: use shared Trion DDR integration - #771

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enjoy-digital merged 2 commits into
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efinix-trion-ddr-followup
Jul 27, 2026
Merged

targets/efinix_t120: use shared Trion DDR integration#771
enjoy-digital merged 2 commits into
masterfrom
efinix-trion-ddr-followup

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Summary

  • use the shared LiteX Trion DDR integration for the T120 development kit
  • keep the board-specific DDR pin and timing description in the platform
  • refresh the generated board inventory after the FireAnt clock-default cleanup

This carries the remaining changes from #769 onto master: #769 was merged into #768's feature branch after #768 itself had already been merged.

Depends on enjoy-digital/litex#2546.

Validation

  • PYTHONPATH=/tmp/litex-efinix-trion-ddr pytest -q test/test_targets.py::TestTargets::test_efinity_targets
    • 1 passed, 10 subtests passed
  • full T120 Efinity 2025.1 synthesis, place-and-route, and bitstream generation
    • system 75MHz setup slack: +2.001ns
  • generated DDR interface XML matches the previous target implementation apart from timestamps
  • python3 .github/scripts/generate_board_inventory.py --check
  • git diff --check

Replace the target-local Efinity XML, pseudo-AXI wiring, and memory mapping with the reusable LiteX Trion DDR core. Keep the board's LPDDR3 preset and timing data in the platform and generate its dedicated 400MHz reference clock with the standard Trion PLL helper.\n\nThis depends on LiteX commit 4ae619c0c (ram/efinix: add shared Trion DDR integration).
Update the generated FireAnt system-clock entry after aligning the target default with the platform clock.
@enjoy-digital
enjoy-digital merged commit 7d0988d into master Jul 27, 2026
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